1. Field of the Invention
The present invention generally relates to digital circuits. More particularly, the present invention relates to the field of circuit architectures for implementing decimation algorithms.
2. Related Art
The technology environment for digital signal processing (DSP) is rapidly changing. DSP performance continues to increase at a fairly constant rate across the industry, and the complexity of DSP peripherals is also expanding. The performance goal of a DSP architecture is to perform as many arithmetic operations as possible in the smallest number of clock cycles. But whereas DSP-centric applications have traditionally employed processors designed for DSP tasks, a complementary, and competing, technology has emerged. Microcontroller suppliers are offering DSP-specific functionality to their architectures.
The analog-to-digital converter (ADC) converts an external analog signal (typically relative to voltage) to a digital representation. Devices such as a microcontroller or DSP processor that have a ADC can be used for instrumentation, environmental data logging, or any other application that lives in an analog world. An overwhelming variety of ADCs exist on the market today, with differing resolutions, bandwidths, accuracies, architectures, packaging, power requirements, and temperature ranges, as well as hosts of specifications, covering a broad range of performance needs.
One popular ADC architecture is the delta-sigma (or sigma-delta) ADC. FIG. 1 illustrates a conventional delta-sigma ADC 100. As illustrated in FIG. 1, the conventional delta-sigma ADC 100 has an analog block (not shown) which performs the analog-to-digital conversion and generates an output stream of 1s (or high) and 0s (or low). Moreover, the conventional delta-sigma ADC 100 has a filter 20 which converts the output 10 of the analog block (not shown) into a digital value 50 having a format suitable for the microcontroller, DSP processor, etc.
The filter 20 includes a (1 bit to Y bits) converter 30 and a conventional decimator 40. The (1 bit to Y bits) converter 30 generates a Y-bit output of +1 values or xe2x88x921 values, depending on whether the output 10 of the analog block (not shown) is 1 or 0 (high or low).
The conventional decimator 40 performs a decimation algorithm using a plurality of discrete circuit stages 50A, 50B, and 50C which are synchronously clocked with the signal CLK. Typically, these discrete circuit stages 50A, 50B, and 50C perform either an integration operation or a differentiation operation. Moreover, each of the discrete circuit stages 50A, 50B, and 50C typically includes an adder and at least one register for implementing an accumulator-type of circuit. The circuit architecture for the conventional decimator 40 is inefficient in terms of circuit area and cost. Moreover, the circuit architecture for the conventional decimator 40 does not provide flexibility to change the decimation algorithm once the conventional decimator 40 had been fabricated.
A new architecture for implementing a digital algorithm such as a decimation algorithm is described. The new decimator circuit is well suited for digital circuits such as a delta-sigma (or sigma-delta) analog-to-digital converter. In particular, the new decimator circuit incorporates a general purpose architecture which enables a wide range of flexibility to change and modify the decimation algorithm performed by the decimator circuit. Moreover, the new decimator circuit can be fabricated in a smaller chip area than previously possible.
Instead of having multiple discrete circuit stages as in the conventional decimator circuit, the decimator circuit of the present invention includes a multiplexer, an adder, and a random access memory (RAM), whereas a plurality of signals control the operation of the multiplexer, the adder, and the RAM such that in a clock cycle at least a portion of a stage of the decimation algorithm is performed. In an embodiment, a state machine is operative to generate the plurality of signals for controlling operation of the multiplexer, the adder, and the RAM. Alternatively, a controller is operative to generate the plurality of signals for controlling operation of the multiplexer, the adder, and the RAM.